Summary
As a manager in the RTL/FE CAD team, you have the opportunity to shape the future of chip design and impact Apple engineers who develop the next generation of Apple products! You will lead a high-impact team that develops software solutions used by thousands of RTL design and integration engineers globally across all chip families (iPhone, iPad, Mac, Apple Watch, and more).

In this role, you will be a key catalyst in transforming front-end hardware design into a modern, agile discipline. You will spearhead the transition to agentic workflows—redefining how RTL and integration teams operate in the AI era. This role combines deep knowledge of RTL/FE flows with modern software engineering practices, people leadership, and a transformative vision for engineering methodology.

Description
You will lead, grow, and inspire a team of engineers driving critical tools across the RTL/FE space, including RTL connectivity, SoC assembly, static sign-off checks (Lint, CDC, RDC), cloud-native services, and CI/CD pipelines.

Beyond delivering core CAD solutions, you will champion a strategic shift toward agentic design flows. You will guide your team and partner organizations in adopting agile, iterative design practices powered by autonomous agents and AI-assisted tooling. Your work will directly redefine engineering methodologies—accelerating design velocity, eliminating manual bottlenecks, and establishing new standards for quality and sign-off readiness. Prior hands-on experience and proven leadership in agentic systems, AI-augmented engineering, or agile hardware transformation will be essential in navigating this shift.

Responsibilities

• People Leadership: Lead, mentor, and grow a team of ~20 CAD engineers, driving talent acquisition, technical mentorship, performance management, and career development.
• Agentic Flow & Methodology Transformation: Drive the team and broader RTL/FE community toward agentic workflows. Act as an organizational change agent, pioneering modern, agile methodologies that transform daily design and integration practices.
• LLM Harness & Agentic Tooling: Own the architecture and execution of the LLM harness for RTL/FE flows (e.g., autonomous violation triage for Lint/CDC/RDC, intelligent connectivity synthesis, and design assist agents). Establish rigorous benchmarks to continually evaluate and elevate workflow accuracy and autonomy.
• RTL Integration & Connectivity Tooling: Own end-to-end RTL integration tools, including connectivity generation, SoC assembly automation, IP packaging, and structural checks.
• Static Sign-off Checks: Drive methodology, deployment, waiver governance, and sign-off metrics for Lint, CDC, RDC, and related static verification domains.
• Roadmap & Milestone Alignment: Define strategic roadmaps and near-term execution plans aligned with multi-project tapeout milestones and long-term organizational goals.
• Stakeholder & EDA Vendor Partnership: Collaborate closely with RTL design and integration leads to turn evolving design challenges into robust software solutions. Partner with EDA vendors to resolve escalations and influence tool roadmaps.
• Software Excellence: Champion software engineering best practices, modern Python development, scalable cloud architectures, and robust CI/CD infrastructure within CAD.
  
  

Minimum Qualifications

• 7+ years of experience as a people manager leading engineering teams.
• BSc/MSc in Electrical Engineering, Computer Engineering, Computer Science, or equivalent.
• Proven track record in RTL design, design integration, or RTL/FE CAD across complex SoC projects.
• Strong software engineering foundation, including system architecture, algorithms, data structures, and modern software design principles.
• Demonstrated experience driving workflow automation, process modernization, or agile transformation within hardware/CAD environments.
• Outstanding communication, collaboration, and stakeholder management skills with the ability to influence cross-functional technical direction.
• Solid grasp of the front-end chip design flow: SystemVerilog/Verilog, RTL integration, static checks (Lint, CDC, RDC), synthesis, and simulation.
  
  

Preferred Qualifications

• Prior expertise designing, deploying, or evaluating agentic workflows, LLM harnesses, or AI-assisted development tools in hardware design or software engineering.
• Experience pioneering agile methodologies in silicon design (e.g., continuous integration for hardware, rapid iteration cycles, automated regressions).
• Hands-on experience with production RTL connectivity tools and SoC top-level assembly flows.
• Strong modern Python expertise (AsyncIO, FastAPI, Pydantic, SQLAlchemy) and experience building distributed, cloud-native backend services.
• Proven success managing relationships with major EDA vendors and driving large-scale tool adoption.
  
  

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Role Number: 200692786-6109