Verification Engineer | Holon

Mertens Malam Team is hiring a Verification Engineer for a leading organization in Holon.

The role includes developing Verification environments using UVM methodology for FPGA across a variety of technological projects in areas such as signal processing, Controllers, and more.

Responsibilities:

Develop Verification environments using UVM methodology

Define, architect, and develop Verification environments from Block Level to Full-Chip

Work with UVM, SystemVerilog, FPGA, ASIC, RTL, Python, TCL, Bash/Csh, and Linux

Collaborate with FPGA development teams, System Engineers, and Algorithm Engineers

Requirements:

5+ years of experience in Verification, from Test Plan definition through Coverage

Hands-on experience with UVM methodology and SystemVerilog

Experience developing Verification environments for FPGA/ASIC at Block and Full-Chip levels

Experience with RTL Debugging from Block Level to System Level

B.Sc. in Electrical Engineering, Electronics Engineering, or Computer Science