DevJobs

Senior Design Verification Engineer

Overview
Skills
  • Perl Perl
  • Python Python
  • Shell Shell
  • System Verilog
  • UVM
  • ACE
  • AMBA
  • ARM
  • AXI4+
  • CHI
  • DDR
  • Formal verification
  • PCIE

Speedata is modernizing analytics infrastructure with the first purpose-built ASIC processor, the Analytics Processing Unit (APU), for analytics and AI data workloads. Delivering up to 100x faster Apache Spark performance while cutting infrastructure TCO by 90%, the APU executes analytics operations directly in silicon with seamless integration and no code changes.


We're looking for the best Senior Verification Engineer!

Join us and be a part of a dynamic team, which revolutionizes the parallel processor architecture.


Requirements:

  • BSc in Electronics Engineering or Computer Science
  • 4+ Years of industry experience in verification, full chip dev. cycle.
  • Experience with System Verilog and UVM methodology - MUST


Advantages

  • M.Sc. in Electronics Engineering or Computer Science
  • Working experience with Formal verification
  • Scripting skills in Python/Perl/shell
  • Hands-on experience with two or more of the following :
  • PCIE (Gen5 and above).
  • DDR (v4 and above).
  • AMBA protocol family, (inc. AXI4+, ACE/CHI)
  • ARM core architecture.

Speedata