DevJobs

Senior VLSI Designer

Overview
Skills
  • Verilog
  • CDC
  • Synthesis
  • SystemVerilog
  • Timing Analysis

We are looking for brilliant VLSI Design engineers that can quickly join a very promising and exciting startup company and take part in and contribute to developing a complex and challenging chip.


*2 Job Locations: Primary- Kiryat Gat, Secondary- Givatayim*


Required Experience:

  • 5+ years of chip design development
  • Experience in logic design and debug
  • Knowledgeable in frontend design fundamentals, flows and tools
  • Experience in back-end report review and implementing timing problems.

Required Skills:

  1. Strong technical skills
  2. Quick learner
  3. Independent
  4. Good communications skills
  5. Extensive knowledge in Verilog is a must
  6. Strong knowledge in logic design fundamentals including backend reports analysis is a must
  7. Knowledge in CDC, synthesis and timing analysis
  8. Knowledge in advanced verification methodologies (system Verilog) – an advantage


Required Education:

  1. BSEE or MSEE in Electrical engineering
Xsight Labs