DevJobs

20371 - RTL Design Engineer

Overview
Skills
  • Perl Perl
  • Python Python
  • Cadence
  • Mentor
  • Synopsys
  • SystemVerilog
  • AMBA
  • AXI
  • DDR
  • PCIe
  • Tcl
Job description:

 

 

In this role, you will be responsible for defining, implementing, and optimizing digital logic designs at the Register Transfer Level (RTL) for complex ASIC/SoC systems.

You will work closely with architecture, verification, physical design, and validation teams to deliver high-performance, power-efficient, and functionally robust designs. 

 

 

Responsibilities:

 

  • Translate architectural specifications into efficient and synthesizable RTL designs (SystemVerilog).
  • Develop detailed microarchitecture specifications for functional blocks or subsystems.
  • Integrate IP blocks and ensure seamless connectivity and data flow across the SoC.
  • Run design checks (lint, CDC, synthesis readiness) and support backend implementation.
  • Collaborate with verification teams to define test plans, review coverage, and debug design issues.
  • Support validation and bring-up teams during silicon bring-up and debug phases.
  • Optimize designs for power, area, and timing while maintaining functional integrity.

 

Profile description:

 

 

Requirements:

 

  • B.Sc./M.Sc. in Electrical Engineering, Computer Engineering, or related field.
  • 3+ years of experience in digital logic or RTL design for ASIC/SoC projects.
  • Strong proficiency in SystemVerilog.
  • Solid understanding of digital design fundamentals (FSMs, pipelining, arbitration, clock/reset domain handling, etc.).
  • Experience with EDA tools for simulation, synthesis, and linting (e.g. Synopsys, Cadence, Mentor).
  • Familiarity with low-power design techniques, timing analysis, and interface protocols (e.g., AXI, AMBA, PCIe, DDR).
  • Excellent problem-solving skills, attention to detail, and ability to work in a cross-functional environment.
  • Experience with SoC-level integration and debug. - Advantage.
  • Knowledge of scripting languages (Python, Perl, or Tcl) for automation. - Advantage.
  • Exposure to FPGA prototyping or emulation environments. - Advantage.
  • Understanding of hardware/software interaction and system-level architecture. - Advantage.

 

 

Why should you join us? 

 

  • Grow your career in a stable, innovative environment 

  • Collaborate closely with clients to deliver smart, high-quality solutions 

  • Make an impact in a dynamic, learning-driven environment 

  • Be part of a human, value-driven organization that cares 



We offer:

Why should you join us? 

 

  • Grow your career in a stable, innovative environment 

  • Collaborate closely with clients to deliver smart, high-quality solutions 

  • Make an impact in a dynamic, learning-driven environment 

  • Be part of a human, value-driven organization that cares 

QualiTest Group