Dustphotonics develops cutting-edge technology in Silicon Photonics, revolutionizing connectivity and communication in data centres.

Silicon photonics is becoming a standard technology used for high-performance systems, solving challenges of performance, integration, power, and cost.

This technology is growing rapidly also in other markets such as Healthcare, LIDARs, and other sensors.

At Dustphotonics, we are looking to solve difficult problems, smartly and simply, by thinking out of the box, leveraging the knowledge and know-how of the team members, and working as a team to create Magic.

Our Company culture is characterized by accountability for our ethics, and for being fair to every employee, customer, supplier, and partner.

We believe we must work hard and have fun on the way to success.

We are looking for a Photonics Design Engineer (Active Devices) with proven, hands-on experience designing, simulating, and measuring active

silicon-photonics components (e.g., modulators, phase shifters, photodiodes).

Requirements:

 M.Sc. (or higher) in Photonics, Electrical Engineering, Physics, Optoelectronics, or

related.

 Hands-on with active optoelectronic devices is required: design + simulation and

measurement/characterization.

 Solid grasp of photonic/device physics (e.g., carrier-depletion/thermal phase shifters,

PN/PIN modulators, Ge or III-V PDs).

 Proficiency with FDTD/EME/mode solvers and circuit-level simulators; ability to

build/fit compact models.

 Strong analytical/problem-solving skills; comfort with data analysis in Python/Matlab

and version control (git).

 Clear communication; effective teamwork.

Preferred Skills

 Experience with SiPh PDKs, gdsfactory/KLayout, and DRM/DRC flows.

 Circuit-/system-level simulation (e.g., INTERCONNECT/Caphe) and CML/compact-

model extraction.

 Practical lab experience: high-speed EO/IV/OP measurements, fixture de-embed,

TDR/TDT/S-parameters.

Responsibilities:

 Design and model active Silicon Photonics devices; own specs, compact models,

and layout intent.

 Drive design for manufacturability: analyze performance across

process/voltage/temperature corners and wafer variability; run Monte-Carlo/tolerance

studies.

 Build scripted, parametric simulation flows (sweeps/optimization) and extract

figures of merit (EO S21, Vπ·L, responsivity, dark current, bandwidth, IL).

 Plan and execute lab/wafer-level measurements; close the model-to-silicon loop

by comparing data to simulations and updating models.

 Collaborate with process, test, and packaging teams on masks, runsets, and

DFT/DFM reviews.