Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Tel Aviv, Israel; Haifa, Israel.Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 5 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog.
• Experience with logic synthesis techniques to optimize RTL code, performance and power as well as low-power design techniques.
• Experience in logic design and debug with Design Verification (DV).
• Experience with design sign-off and quality tools (e.g., Lint, CDC, etc.).
  
  

Preferred qualifications:

• Experience in scripting languages like Python or Perl.
• Knowledge of high performance and low power design techniques.
• Knowledge of assertion-based formal verification.
• Knowledge of System-on-a-Chip (SoC) architecture.
• Domain knowledge in one of these areas: PCIe, UCIe, DDR, AXI, ARM processors.
  
  

About The Job

Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

Responsibilities

• Define the SoC/block level design document such as interface protocol, block diagram, transaction flow, pipeline etc.
• Perform Register-Transfer Level (RTL) development (e.g., coding and debug in Verilog, SystemVerilog), function/performance simulation debug and Lint/CDC/FV/UPF checks.
• Participate in synthesis, timing/power closure and ASIC silicon bring-up.
• Participate in test plan and coverage analysis of the block and SoC level verification.
• Communicate and work with multi-disciplined and multi-site teams.
  
  
  

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .