DevJobs

Physical Design Backend Engineer

Overview
Skills
  • ASIC Backend design ꞏ 3y
  • chip synthesis ꞏ 3y
  • DFT insertion ꞏ 3y
  • Synthesis ꞏ 3y
  • Synopsys flow ꞏ 3y
  • STA Signoff ꞏ 3y
  • STA ꞏ 3y
  • Place & Route ꞏ 3y
  • PnR tool and flows ꞏ 3y
  • RTL to GDSII full flow implementation ꞏ 3y
  • physical signoff concepts and tools
  • UPF concepts
  • Synopsys Primetime
  • Synopsys DC
  • small geometry process nodes
  • advanced DFT flows & tools
  • low-power
  • logic equivalence tools
  • IR drop
  • ICC2
  • Fusion-Compiler
  • FC
  • Ansys Redhawk

Nuvoton Technology, a semiconductor company in Herzliya, is looking for a Backend Design engineer to join its Physical Design department!

As a Physical Design engineer, you will take a significant part of the full chip development flow, from RTL to GDS.

You will be responsible for Synthesis, Place & Route, STA, DFT insertion and more.

Note that we are using Synopsys flow.


Requirements:

  • BSc. in Electrical/Communication/Computer engineering from a known university
  • 3+ years of experience in ASIC Backend design
  • Experience with small geometry process nodes (40 nm and below) – Advantage
  • Familiarity with RTL to GDSII full flow implementation
  • Experience in chip synthesis - Must (Synopsys DC/FC – Advantage)
  • Familiarity with advanced DFT flows & tools - Advantage
  • Experience in STA Signoff - Must (Synopsys Primetime – Advantage)
  • Experience in PnR tool and flows (ICC2/Fusion-Compiler – Advantage)
  • Familiarity with IR drop - (Ansys Redhawk – Advantage)
  • Familiarity with logic equivalence tools – Advantage
  • Familiarity with low-power / UPF concepts – Advantage
  • Familiarity with physical signoff concepts and tools - Advantage
Nuvoton