Role Description

This is a full-time on-site role for an RTL Designer located in Haifa District, Israel. The RTL Designer will be responsible for designing and implementing high-quality digital logic using Verilog/SystemVerilog. The RTL Designer will also collaborate with cross-functional teams to identify business opportunities and provide customized solutions, work closely with ASIC and FPGA design teams to develop and verify RTL.

Qualifications

• Bachelor's/Master's degree in Electrical Engineering or Computer Science or related fields
• At least 3 years of experience with digital logic design using Verilog or SystemVerilog.
• Experience with RTL design, simulation and verification skills
• Familiarity with ASIC and/or FPGA design flow and tools
• Familiarity with one or more of the following fields is an advantage:

* PCIe (Gen5+ a strong advantage)

* CXL (a strong advantage)

* Cache and memory architectures

* CPU architecture

* HW-SW interfaces

• Strong analytical and problem-solving skills
• Good communication skills, ability to work in a team, and fluency in English
• Self-motivated, goal-oriented, and a strong desire to learn and excel