As a Backend engineer, you will take a significant part of the full chip development flow, from RTL to GDS. You will be responsible for Synthesis, Floor Planning, Place & Route, STA, DFT architecture and more.

Requirements:

· BSc. in Electrical/Communication/Computer engineering from a known university

· 3+ years of experience in ASIC Backend design

· Experience in STA Signoff - Must (Synopsys Primetime – Advantage)

· Familiarity with RTL to GDSII full flow implementation

· Familiarity with advanced DFT flows & tools - Advantage

· Experience with small geometry process nodes

· Familiarity with ICC2 tool – Advantage