Mertens – MalamTeam is hiring a Verification Engineer for a leading organization in Holon

Role Overview

Develop UVM-based verification environments for FPGA projects, including signal processing and controllers. The role involves designing and implementing verification environments from Block Level to Full-Chip, working with SystemVerilog, RTL, Python, TCL, Bash/Csh, and Linux in collaboration with FPGA, system, and algorithm engineering teams.

Requirements

• 5+ years of Verification experience, from test planning through coverage analysis

• Hands-on experience with UVM methodology and SystemVerilog

• Experience developing FPGA/ASIC verification environments at Block and Full-Chip levels

• Strong RTL debugging skills, from Block to System Level

• B.Sc. in Electrical Engineering, Electronics Engineering, or Computer Science