Verification Engineer | Holon

Mertens Malam Team is hiring a Verification Engineer for a leading organization in Holon.

Key Responsibilities:

Develop FPGA Verification environments using UVM methodology across various technology projects, including signal processing, controllers, and more

Define, architect, and develop Verification environments from Block Level to Full-Chip

Work with UVM, SystemVerilog, FPGA, ASIC, RTL, Python, TCL, Bash/Csh, and Linux

Collaborate with FPGA development teams, System Engineers, and Algorithm Engineers

Requirements:

At least 5 years of experience in Verification, from Test Plan definition through Coverage

Hands-on experience with UVM methodology and SystemVerilog

Experience developing FPGA/ASIC Verification environments at Block and Full-Chip levels

Experience in RTL Debugging from Block to System Level

B.Sc. degree in Electrical Engineering, Electronics Engineering, or Computer Science