About RAD:

RAD is a global leader in networking edge solutions, serving communications service providers and critical-infrastructure operators in more than 150 countries with Carrier Edge, 5G xHaul, industrial IoT and critical operational network solutions.

Behind those products sits a strong in-house silicon capability. RAD designs and verifies its own ASIC and FPGA devices, including network processors and high-speed network interface solutions that power its core products. Our verification group, based in Tel Aviv and Be'er Sheva, owns the quality of these designs from the first specification through tapeout, and works hand in hand with architecture, design, software and validation teams.

The Role:

We are looking for a Verification Lead to take technical ownership of verification for our next-generation telecom ASICs. This is a hands-on technical leadership role: you will define the verification strategy, architect modern SystemVerilog/UVM environments, and lead a team of verification engineers through full chip cycles, from spec to tapeout and silicon bring-up.

You will be the go-to technical authority for verification methodology, set the bar for quality and coverage closure, and help shape how the group adopts new tools and approaches.

Location: Tel Aviv or Be'er Sheva.

What You'll Do:

• Lead the technical verification effort for complex, high-speed telecom ASICs and their subsystems.
• Define verification strategy, test plans and coverage models, and drive them to sign-off.
• Architect and build scalable, reusable SystemVerilog/UVM testbenches, including VIP integration.
• Apply coverage-driven, constrained-random and assertion-based verification (SVA), and formal methods where they add value.
• Lead block, subsystem and SoC-level verification, including gate-level simulation (GLS) and emulation flows.
• Own coverage closure, bug tracking and tapeout readiness reviews.
• Mentor and guide verification engineers through code and plan reviews, and set team best practices.
• Work closely with architecture, RTL design, software and lab validation teams, and support post-silicon debug.
• Drive modernization of the verification flow: automation, regression management, CI and AI-assisted verification.

Requirements:

• B.Sc. or M.Sc. in Electrical Engineering, Computer Engineering or a related field.
• 7+ years of hands-on ASIC verification experience.
• Proven end-to-end ASIC experience, with several full cycles through tapeout.
• Expert-level SystemVerilog and UVM, including building testbenches from scratch.
• Strong background in coverage-driven, constrained-random and assertion-based verification (SVA).
• Experience as a technical lead: owning verification plans, guiding engineers and driving closure.
• Scripting for automation and regressions (Python preferred; Bash/Tcl), in a Linux environment.
• Excellent debugging, communication and teamwork skills.