Verification Engineer | Holon

Mertens Malam Team is hiring a Verification Engineer for a leading organization in Holon.

The role includes developing UVM-based Verification environments for FPGA across a variety of technology projects in Signal Processing, Controllers, and additional domains, from definition and architecture through Block Level and Full-Chip Verification.

Responsibilities:

Develop Verification environments using UVM methodology for FPGA

Define and design Verification architecture from Block Level to Full-Chip

Work across technology projects in Signal Processing, Controllers, and additional domains

Work with UVM, SystemVerilog, FPGA, ASIC, RTL, Python, TCL, Bash/Csh, and Linux

Collaborate with FPGA development teams, System Engineers, and Algorithm Engineers

Requirements:

5+ years of Verification experience, from Test Plan definition through Coverage

Hands-On experience with UVM methodology and SystemVerilog

Experience developing Verification environments for FPGA/ASIC at Block and Full-Chip levels

Experience with RTL Debugging from Block Level through System Level

B.Sc. degree in Electrical Engineering, Electronics Engineering, or Computer Science