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QualityAI is the leading AI-first quality engineering company. We deliver end-to-end quality management services across the business and technology life cycle for enterprise customers who need certainty at Go-Live.
We build and test services and products using AI, working across data, models, platforms, devices, and infrastructure to ensure those systems perform as expected at scale
We are looking for an experienced Senior Formal Verification Engineer to join our CPU development team as an XWF (Extended Workforce) member. In this role, you will be responsible for driving the formal verification of CPU cache designs, ensuring comprehensive verification coverage and proof closure based on the project's verification plan.You will work closely with CPU architects, design engineers, and the verification team to verify complex microarchitecture features and solve challenging verification problems related to modern CPU design.
Responsibilities
Translate formal verification requirements from the verification plan into complete formal proofs for the Design Under Test (DuT)
Develop, implement, and maintain formal verification environments and methodologies for CPU cache verification
Create and debug SystemVerilog Assertions (SVA) to verify functional correctness.Analyze proof failures, identify root causes, and collaborate with design engineers to resolve issues
Drive formal verification closure while ensuring high-quality verification coverage.Debug complex microarchitectural behaviors, including branch prediction and memory concurrency scenarios
Work closely with CPU architects and RTL designers to verify new features throughout the development lifecycle
Requirements
10+ years of experience in Formal Verification
Extensive hands-on experience with Cadence JasperGold or equivalent formal verification tools
Strong expertise in SystemVerilog Assertions (SVA) and property-based verification
Deep understanding of CPU microarchitecture, including pipelines, cache architecture, branch prediction, and memory concurrency
Proven ability to translate verification requirements into complete formal proofs
Strong debugging and analytical skills with the ability to solve complex verification challenges
Excellent communication and collaboration skills
Preferred Qualifications:
Experience verifying CPU IP or other complex processor subsystems
Experience working on high-performance CPU or SoC development projects
Familiarity with industry-standard verification methodologies and best practices
Why should you join us?
QualityAI is the leading AI-first quality engineering company. We deliver end-to-end quality management services across the business and technology life cycle for enterprise customers who need certainty at Go-Live.
We build and test services and products using AI, working across data, models, platforms, devices, and infrastructure to ensure those systems perform as expected at scale
We are looking for an experienced Senior Formal Verification Engineer to join our CPU development team as an XWF (Extended Workforce) member. In this role, you will be responsible for driving the formal verification of CPU cache designs, ensuring comprehensive verification coverage and proof closure based on the project's verification plan.You will work closely with CPU architects, design engineers, and the verification team to verify complex microarchitecture features and solve challenging verification problems related to modern CPU design.
Responsibilities
Translate formal verification requirements from the verification plan into complete formal proofs for the Design Under Test (DuT)
Develop, implement, and maintain formal verification environments and methodologies for CPU cache verification
Create and debug SystemVerilog Assertions (SVA) to verify functional correctness.Analyze proof failures, identify root causes, and collaborate with design engineers to resolve issues
Drive formal verification closure while ensuring high-quality verification coverage.Debug complex microarchitectural behaviors, including branch prediction and memory concurrency scenarios
Work closely with CPU architects and RTL designers to verify new features throughout the development lifecycle
Requirements
10+ years of experience in Formal Verification
Extensive hands-on experience with Cadence JasperGold or equivalent formal verification tools
Strong expertise in SystemVerilog Assertions (SVA) and property-based verification
Deep understanding of CPU microarchitecture, including pipelines, cache architecture, branch prediction, and memory concurrency
Proven ability to translate verification requirements into complete formal proofs
Strong debugging and analytical skills with the ability to solve complex verification challenges
Excellent communication and collaboration skills
Preferred Qualifications:
Experience verifying CPU IP or other complex processor subsystems
Experience working on high-performance CPU or SoC development projects
Familiarity with industry-standard verification methodologies and best practices
Why should you join us?
QualityAI is the leading AI-first quality engineering company. We deliver end-to-end quality management services across the business and technology life cycle for enterprise customers who need certainty at Go-Live.
We build and test services and products using AI, working across data, models, platforms, devices, and infrastructure to ensure those systems perform as expected at scale
We are looking for an experienced Senior Formal Verification Engineer to join our CPU development team as an XWF (Extended Workforce) member. In this role, you will be responsible for driving the formal verification of CPU cache designs, ensuring comprehensive verification coverage and proof closure based on the project's verification plan.You will work closely with CPU architects, design engineers, and the verification team to verify complex microarchitecture features and solve challenging verification problems related to modern CPU design.
Responsibilities
Translate formal verification requirements from the verification plan into complete formal proofs for the Design Under Test (DuT)
Develop, implement, and maintain formal verification environments and methodologies for CPU cache verification
Create and debug SystemVerilog Assertions (SVA) to verify functional correctness.Analyze proof failures, identify root causes, and collaborate with design engineers to resolve issues
Drive formal verification closure while ensuring high-quality verification coverage.Debug complex microarchitectural behaviors, including branch prediction and memory concurrency scenarios
Work closely with CPU architects and RTL designers to verify new features throughout the development lifecycle
Requirements
10+ years of experience in Formal Verification
Extensive hands-on experience with Cadence JasperGold or equivalent formal verification tools
Strong expertise in SystemVerilog Assertions (SVA) and property-based verification
Deep understanding of CPU microarchitecture, including pipelines, cache architecture, branch prediction, and memory concurrency
Proven ability to translate verification requirements into complete formal proofs
Strong debugging and analytical skills with the ability to solve complex verification challenges
Excellent communication and collaboration skills
Preferred Qualifications:
Experience verifying CPU IP or other complex processor subsystems
Experience working on high-performance CPU or SoC development projects
Familiarity with industry-standard verification methodologies and best practices
Why should you join us?