About

RAAAM Memory Technologies Ltd. is an innovative embedded memory solutions provider, that delivers the most cost-effective on-chip memory technology in the semiconductor industry. Our products solve the embedded memory density and energy challenges of the CMOS semiconductor industry and enables industry growth for applications in the areas of AR/VR, Machine Learning (ML), Internet-of-Things (IoT) and Automotive.

We offer a dynamic work environment with a growing team of creative and ambitious engineers that strive for innovative solutions that are readily applicable to a variety of application domains.

Job description

Physical Design Engineer responsible for the implementation and signoff of RAAAM’s next-generation embedded memories test chips across a variety of advanced CMOS technologies.

Responsibilities

●       Execute various Place and Route (P&R) tasks from RTL to GDSII.

●       Perform comprehensive design signoff, including STA, EMIR, DRC, and LVS.

●       Work extensively with a variety of process nodes, focusing on advanced technologies down to 2nm and beyond.

●       Automate design and physical verification flows to improve efficiency.

●       Collaborate closely with circuit design and integration teams.

Qualifications

●       2+ years of experience in Physical Design (RTL to GDS).

●       Hands-on experience with Cadence EDA tools, specifically Genus and Innovus.

●       Strong understanding of physical design signoff processes (STA, DRC, LVS).

●       Independent in his work and strives to bring results

●       High proficiency in scripting, automation, and Linux environments (e.g., TCL, Python, Bash).

●       MSc./ BSc. degree in Electrical / Computer Engineering.

Location

●       Israel or Switzerland

Full / Part Time

●       Full time