DevJobs

SoC Test Engineer Lead, Google Cloud

Overview
Skills
  • Python Python
  • ASIC
  • ATE
  • ATPG
  • Exensio
  • JMP
  • MBIST
  • Memory Repair
  • RTL
  • SLT
  • YieldExplorer
Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Tel Aviv, Israel; Haifa, Israel.Minimum qualifications:

  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
  • 10 years of experience in product engineering or test engineering.
  • 3 years of experience in people management, developing employees.
  • Experience with product engineering, supply chain data analytics or diagnostics for manufacturing or New Product Introduction (NPI).

Preferred qualifications:

  • Experience with industry standards, design tools, and DFT best practices, including at-speed TDF, ATPG, MBIST, Memory Repair, diagnostic tools, yield improvement.
  • Experience with product engineering, supply chain data analytics and diagnostics for High Volume Manufacturing and NPI.
  • Experience evaluating customer returns with ATE and SLT, identifying coverage gaps, developing incremental structural and functional patterns to address quality issues, Statistical analysis (e.g., JMP), Yield Management Systems (e.g., Exensio, YieldExplorer, JMP), and Python for data analytics.
  • Understanding of skew lot definition, data collection, characterization, data analysis and report.

About The Job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Do you want to be part of Google’s next generation of data centers? Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. As part of our server chip design team, you will use your ASIC design experience to be part of a team that creates the SoC VLSI design cycle from start to finish. You will collaborate closely with design and verification engineers in active projects, creating architecture definitions with RTL coding, and running block level simulations.

In this role, you will contribute in all phases of complex application-specific integrated circuit (ASIC) designs from design specification to production. You will collaborate with members of architecture, software, verification, power, timing, synthesis and etc. to specify and deliver high quality SoC/RTL. You will solve technical problems with innovative micro-architecture and practical logic solutions, and evaluate design options with complexity, performance, power and area in mind.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Responsibilities

  • Develop and implement strategies for high volume manufacturing of SoC products, including troubleshooting, ATE test coverage optimization, Defective Parts Per Million (DPPM) reduction, test cost reduction, power and performance assurance, and product data integration and correlation between system, ATE, and SLT.
  • Drive interactions with wafer fabs and Outsourced Semiconductor Assembly and Tests (OSATs), own and drive checkpoints for key quality metrics.
  • Drive volume ramp and mass production through test program releases, volume data analytics, lot disposition, extended test time reduction, yield improvement, and Return Merchandise Authorization (RMA) handling.
  • Support setup and maintenance of test, diagnosis, and yield analysis infrastructure, including RMA support.
  • Collaborate with cross-functional teams across the globe including ATE and SLT Test Engineering, Quality and Reliability, Packaging, Supplier Management and Operations to build, deploy, and maintain a high volume manufacturing screening solution.


Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .
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