Summary
Design Verification (DV) Engineer positions at Apple Israel (Herzliya, Haifa, and Jerusalem). While the specific teams vary—ranging from Wireless SoC and Memory Signal Processing (MSP) to Pixel/Media IPs and CPU/SoC Memory Subsystems—the fundamental expectations remain consistent.

Description
As a Design Verification Engineer, you will be responsible for ensuring "bug-free first silicon" for complex IP and SoC designs. You will drive all phases of pre-silicon verification, from defining methodologies and test plans to RTL freeze and tape-out sign-off. These roles are highly collaborative, requiring close interaction with architecture, design, and software teams across global sites.

Responsibilities

• Architect and develop scalable, portable verification environments, including UVM-based testbenches, protocol monitors, agents, and checkers.
• Define detailed test and coverage plans based on micro-architecture specifications and extract features for DV attributes.
• Create and simulate test scenarios, perform advanced debugging, and conduct end-to-end simulations of data/control paths.
• Drive regression and coverage analysis (metric-driven verification) to ensure the highest quality, productivity, and time-to-market.
• Partner with architects and designers from the early stages of feature definition to influence IP/SoC specifications.
• Apply formal verification, hardware acceleration, and power/performance (NLP) analysis where applicable.
  
  

Minimum Qualifications

• Ranges from 2+ to 7+ years in digital logic design verification (IP or SoC level).
• B.Sc. or M.Sc. in Electrical Engineering, Computer Engineering, or Computer Science.
• Expert-level knowledge of SystemVerilog and UVM (or high-level C/C++ in lieu of UVM for specific teams).
• Proficiency in Python, Perl, or TCL for automation and tool development.
• Extensive experience with simulators, waveform viewers, and coverage collection tools.
  
  

Preferred Qualifications

• Strong interpersonal skills to interface with diverse groups across multiple geographies.
• Ability to remain productive under tight schedules and prioritize tasks in a fast-paced environment.
• Proven creative thinking and a "deep system-level" approach to finding architecture bugs.
  
  

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Role Number: 200654645-1451