DevJobs

FPGA design engineer

Overview
Skills
  • Python Python
  • Xilinx ꞏ 3y
  • FPGA ꞏ 3y
  • RTL
  • Wireless Communication
  • Vivado
  • Verilog
  • Timing Closure
  • Timing Analysis
  • SystemVerilog
  • Synthesis
  • Simulation
  • SDK
  • ARM
  • Place and Route
  • MicroBlaze
  • Lab Testing Equipment
  • Lab FPGA Debug
  • Digital Signal Processing
  • Design Verification
  • Debugging

Key responsibilities:

· Design FPGA micro-architecture

· FPGA implementation in RTL of signal processing algorithms

· Modifying existing FPGA designs to add features and enhance functionality

· Integration with Micro blaze and ARM processors

· Writing technical documents, testing and interfaces

· Simulation and debugging

· Design verification and integration

Requirements:

· B.Sc.\M.Sc. in Electrical Engineering

· 3+ years of experience in FPGA development (Xilinx)

· Experience in wireless communication and digital signal processing

· Experience in writing advanced simulations using SV and Python

· Experience with Xilinx design flow and tools (Vivado ,SDK)

· Experience with FPGA coding (Verilog/SV preferred), synthesis, place and route, timing analysis and timing closure

· Experience with lab FPGA debug

· Experience with lab testing equipment for communication systems

· Excellent collaboration and communications skills

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