DevJobs

PD Engineer

Overview
Skills
  • Perl Perl
  • Shell Shell
  • Python Python
  • PnR
  • Xtalk
  • Verilog
  • Tcl
  • Synthesis
  • Synopsys
  • STA
  • Cadence
  • Physical Verification
  • LVS
  • IR-Drop
  • HDL
  • EM
  • ECO
  • DRC
Summary

At Apple, we work every single day to craft products that enrich people’s lives. As a member of our Physical Design group, you will take an integral part in bringing large-scale SoCs to life, helping us deliver the next generation of Apple's ground-breaking products. We have an opportunity for an exceptionally talented IP Physical Design Lead to join our dynamic team.

Description

This is a highly visible role where you will own the physical design cycle at the partition, IP, and Chip levels—enabling us to produce fully functional 'first silicon' designs. Do you love working on challenges that no one has solved yet? If you are ready to join the world's leading engineers and work with state-of-the-art design flows, come join our group.

Responsibilities

  • You will be responsible for all phases of pre-silicon development, from initial definition to high-quality tape-out (Netlist to GDSII).
  • Lead block-level Place & Route (PnR), complex floor-planning, partitioning, and the creation of power domains and grid specifications.
  • Develop and validate high-performance, low-power clock network guidelines and distribution.
  • Drive static timing closure (STA), Physical Verification (DRC/LVS), and Electrical/Power analysis (EM, IR-Drop, Xtalk, and Noise).
  • Participate in establishing CAD and physical design methodologies for 'correct-by-construction' designs and assist in flow development for chip integration.
  • Generate and implement ECOs to fix timing, noise, and EM/IR violations while meeting strict area and power constraints.
  • Work closely with logic design teams on SoC architecture and HDL (Verilog) to implement timing fixes and design optimizations.

Minimum Qualifications

  • B.Sc. or M.Sc. in Electrical Engineering or Computer Engineering.
  • 3–7 years of Physical Design experience on high-performance, low-power, large-scale SoCs.
  • Power user of industry-standard PnR and Synthesis tools (Synopsys or Cadence).
  • Deep understanding of physically aware synthesis, extraction, and STA methodologies.
  • Strong programming skills in Tcl, Python, Perl, or Shell scripting.
  • Experience with successful tape-outs in advanced sub-micron process technologies.

Preferred Qualifications

  • Strong interpersonal skills with the ability to interface across various multi-functional groups within the company.
  • A 'game-changing' mindset with the ability to remain productive and focused under tight, demanding schedules.
  • A collaborative spirit that thrives in a high-energy, dynamic engineering environment.

Apple