DevJobs

HW & Verification – Student Position

Overview
Skills
  • Python Python
  • Perl Perl
  • I2C
  • PCIe
  • SPI
  • UART
  • System Verilog
  • TCL
  • Verilog
  • VHDL
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HW & Verification – Student Position

  • Department: R&D
  • Location: Tel Aviv
  • Workplace Type: Hybrid
  • Employment: Student

About Raft

Raft Technologies is revolutionizing global connectivity by harnessing radio frequency cutting-edge Skywave technology to create the world’s fastest low-latency wireless network, pushing the boundaries of communication speed to approach the ultimate limit of light itself. Raft operates ultrafast data links connecting key destinations across continents, with a focus on transatlantic routes, linking major financial hubs worldwide.

This is an opportunity for YOU to join our cutting edge, intriguing field.

About The Position

About the Role

Contribute to both hardware design/bring-up and verification activities. You’ll help prototype and validate board-level designs, write/execute verification test plans, and collaborate with senior engineers across the R&D department to ensure robust hardware/firmware integration.

  • Student position – 2.5 days per week (~20 hours weekly)

Responsibilities

  • Support board bring-up: power sequencing checks, interface validation (UART/I2C/SPI/PCIe as applicable), basic firmware flashing, running full HW platform tests.
  • Develop and execute verification test plans for blocks and subsystems; create test cases and track coverage.
  • Build and run hardware-in-the-loop (HIL) or bench-based validation setups; capture and analyze waveforms with scopes/logic analyzers.
  • Automate tests and data collection with Python. Generate reports and defect tickets with clear repro steps.
  • Collaborate with System, FPGA, SW, Embedded, Algo and Verification teams to debug issues, drive root-cause analysis, and verify fixes.
  • Maintain documentation for test procedures, fixtures, and regression results.

Requirements

  • B.Sc. student in Electrical Engineering (or equivalent field – CE/Physics) from leading universities with emphasis on signal-processing/communication background.
  • At least 1.5 years remaining until graduation
  • VLSI course or similar basic Proficiency.
  • Grade average above 85.
  • Excellent teamwork and independent working abilities.
  • Strong communication skills.

Advantages

  • Knowledge of lab equipment and test procedures
  • Previous experience in HDL langue (VHDL, Verilog, System Verilog)
  • Knowledge with scripting (Perl, Python, TCL etc.)
Raft Technologies