We are looking for a Senior Verification Engineer to join our team

Job Description:

The role includes defining verification strategies, building environments, and ensuring coverage closure for complex designs.

You will work closely with design and architecture teams throughout the full development lifecycle.

Requirements:

• B.Sc./M.Sc. in Electrical Engineering or Computer Engineering
• 7+ years of hands-on experience in VLSI Verification
• Strong knowledge of SystemVerilog and UVM
• Experience with C/C++ and Python or Perl - advantage
• Background in RTL analysis and complex logic verification - advantage

Job number: 1832