abra R&D is seeking for a Verification Engineer.

We are looking for an Adaptable Verification Engineer who can move across blocks and tasks, partner with design/FPGA/architecture, and own floating assignments with partial specs.

Key Responsibilities:

• Build/maintain SystemVerilog/UVM environments; write testbenches, simulations, and regressions.
• Analyze specs → create verification plans; drive debug and bug fixing to closure.
• Track functional/code coverage; document flows and improve team productivity.
• Context‑switch across blocks; support integration and ad‑hoc scripting/automation.

Must‑Haves

• B.Sc. in EE/CE (or related).
• 3+ years verification in ASIC/SoC (4+ preferred).
• Strong SystemVerilog/UVM; experience with Verdi/Questa/VCS.
• Proven self‑learning, flexibility, and ownership of undefined work; clear teamwork/communication.

Nice to Have

• Protocols: AMBA/AXI/AHB, PCIe, Ethernet.
• Scripting: Python, Perl, Tcl.
• Tools: Git, Jira.