DevJobs

VLSI Design Engineer

Overview
Skills
  • Perl Perl
  • Python Python
  • System Verilog ꞏ 2y
  • Verilog ꞏ 2y
  • CDC
  • Clock domain crossing
  • Debugging
  • EDA tools
  • Lint
  • Power management
  • Simulation
  • Synthesis
  • Timing analysis
Who We Are?

We’re building the next Gen. AI Factory, at a leading AI Infrastructure technology company. Our products sit at the core of rack-scale computing and define the performance and scale of AI systems. If you’re driven by solving problems, some don’t yet have names, this is where you want to be.

In this role, you will be:

  • Responsible for definition and micro-architecture of complicated digital blocks
  • Detailed documentation and RTL implementation including running EDA tools (Lint, CDC, simulation, debugging, synthesis and timing analysis)
  • Work closely with verification and architecture team
  • Participate in design methodology and tool automation work as needed

Requirements:

Requirements:

  • B.Sc. in Electrical Engineering
  • Minimum 2 years of experience in logic design from semiconductor companies
  • Knowledge and experience in Verilog and/or System Verilog
  • Knowledge of power management techniques for low power design
  • Familiarity with Clock domain crossing, simulation, debugging, synthesis and timing analysis
  • Knowledge in scripting languages such as Python or Perl – Advantage
  • Very good communication skills
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