Job Details

Job Description:

Develop the logic design, Register Transfer Level (RTL) coding, simulation, and provide DFT timing closure support. Define and Implement SoC main debug Fabrics - TAP and Scan. Develop automatic tools to expedite and improve design and integration. Closely work with Architecture and uArch, Silicon and Manufacturing teams to define new features and improve DFT capabilities - Power, Performance, Test Time, coverage and more. Define validation activities and work with validation owners to increase coverage and design quality. Define IPs DFT requirements to meet SoC needed quality, support IPs integration and validation. Develop HVM ready content, enable it on Pre Si ENV as well as on real Silicon. Dirve Coverage improvement, DPM reduction and faster Content enabling on Silicon.

Qualifications

Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications

• Bachelor’s degree in Electrical Engineering, or related field.
• 5+ years of experience in Design-for-Test (DFT) methodologies.
• 2+ years of hands-on experience with Scan insertion and related flows.
• Proficiency in working in Linux environments.
  
  

Job Type

Experienced Hire

Shift

Shift 1 (Israel)

Primary Location:

Israel, Petah-Tikva

Additional Locations:

Israel, Haifa

Business Group

The Silicon Engineering Group (SIG) is a worldwide organization focused on the development and integration of SOCs, Cores, and critical IPs from architecture to manufacturing readiness that power Intel’s leadership products. This business group leverages an incomparable mix of experts with different backgrounds, cultures, perspectives, and experiences to unleash the most innovative, amazing, and exciting computing experiences.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.