About Us

NeoLogic is a unique fabless semiconductors startup. We develop cutting edge processors to address the ever-increasing workloads of next generation AI data centers.

Role Description

We are looking for an experienced physical backend design manager to join our fast-growing team. The ideal candidate should have hands-on experience of the full ASIC backend flow from RTL to GDS, as well as managerial skills.

What you will be doing?

Build and manage the design team for implementing NeoLogic's next-gen processor using our innovative technology. Your ultimate goal will be to enhance performance per power and area across various targeted workloads.

Qualifications

• B.Sc. in Electrical Engineering, Computer Engineering or related field.
• At least 10 years of proven experience of BE implementation of multi-million instance chips.
• At least 3 years of experience as a team leader or group manager
• Experience with place & route tools and flows (Synopsys / Cadence).
• Experience and understanding of static timing analysis.
• Extensive know-how in floor-planning, power grid distribution, RDL and bumps.
• Experience with advanced CMOS process nodes (5nm/3nm) - advantage
• Experience with I/O ring integration and ESD - advantage
• Extensive understanding of DRC / LVS - advantage