Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Tel Aviv, Israel; Haifa, Israel.Minimum qualifications:

• Bachelor's degree in Electrical Engineering or equivalent practical experience.
• 8 years of experience with design from micro-architecture through implementation with Verilog/SystemVerilog, or VHDL language.
• Experience with chip design flow, chip architecture, design methodologies, physical design, and verification processes.
• Experience working with high speed, lower power design.
• Experience in leading chip development projects and teams.
  
  

Preferred qualifications:

• Master's or PhD degree in Engineering or equivalent practical experience.
• Experience with ASIC design methodologies for front quality checks (e.g., Lint, CDC/RDC, Synthesis, design for testing, ATPG/Memory BIST, UPF, and Low Power Optimization/Estimation).
• Knowledge of advanced high-performance CPU design and architecture.
• Ability to motivate and focus a large collaboration to reach testing goals.
• Excellent communication and facilitation skills.
  
  

About The Job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

In this role, you will oversee the design and development of CPU IP, leading complex blocks design end-to-end—from architecture requirements to tape-out.

Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

Responsibilities

• Own the chip development and execution. Accountable for Quality, Schedule and Performance, Power Area (PPA), being the primary point of contact for day-to-day execution of chip development, Planning and tracking.
• Coordinate work across different disciplines, including design, verification, and testing, to ensure the chip meets all specifications and requirements. Collaborate with the leadership team of each chip project: Technical Program Manager (TPM), Design Verification lead, Physical Design lead (PD), Design for Testing lead, Design lead, and architecture team, to make execution decisions and drive the development process.
• Resolve technical issues that arise during the chip development process. Ensure chip quality by implementing best practices and implementing quality control measures.
• Lead the project development with excellent quality and address issues throughout the design and implementation phases.
  
  
  

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .