DevJobs

Senior Chip Design Engineer

Overview
Skills
  • Python Python
  • SV
  • Verilog
  • HLS
  • SDK
  • UVM
  • Vivado

Hyperspace is cooking something big and we are looking for a Senior Chip Designer Engineer.

How big do you ask?

Well, if you are versed in the world of search then you know that current search technology is reaching its limitation. And today’s technology is not able to answer the demand of today’s market.

This is where Hyperspace comes into the picture and, so can you.

Help us take search to a whole new level.

Bring your genius and your diversity to our workplace. On our end, we promise you won’t have a dull moment at work.

Here are some of the job basics:


Key responsibilities

  • Design micro-architecture for accelerated search workload
  • FPGA implementation in RTL
  • Simulation and debugging
  • Design verification and integration


Skills and qualification

  • B.Sc./M.Sc. in Electrical/Computer Engineering
  • 5+ years of experience in logic design
  • Logic design experience at RTL level (Verilog/SV preferred), synthesis, place and route, timing analysis and timing closure
  • Strong capabilities in system and hardware-level design
  • Experience in writing advanced simulations environments using SV and Python
  • Ability to tackle complex and hard-to-solve problems at hardware level
  • Excellent collaboration and communications skills


Advantages

  • Experience with Xilinx design flow and tools (Vivado ,SDK)
  • Experience in developing designs in HLS
  • Experience in cloud based FPGA instances
  • Experience in Verification methodology (UVM or equivalent)
Hyperspace