D-Fend Solutions values its employees as our greatest asset. Our professionals and subject matter experts, including personnel from elite military intelligence technology units, provide the best possible solutions to our leading customers around the world. We are proud of our impressive presence across different environments and industries, as well as the results we have helped our customers achieve in contending with their counter-drone challenges.

In addition to professional expertise, D-Fend Solutions seeks candidates who will thrive in a fast-moving, innovative and collaborative culture. It helps if you enjoy having fun – our “D-Fenders” are a light-hearted bunch who have stashed rubber ducks all around our headquarters.

Are you interested in working with the world’s leading cyber-takeover counter-drone technology provider?

Join D-Fend Solutions in helping to make the world a safer place by addressing emerging challenges in the dynamic and exciting counter-drone arena!

Scope:

We are looking for a Senior FPGA Engineer for playing a key role in the FPGA discipline of the company.

As part of your position you are expected to take part in:

• Collaboration with a multi-disciplined design team (electrical engineers, systems engineers, SW engineers, etc) to design and integrate challenging DSP FPGA designs for wireless systems.
• Implementation and validation of highly complex designs in either new or existing modular HDL designs.
• Bring up, configuration, characterization, and debugging of new hardware.
• Conducting experimental tests on the latest FPGA and SoC evaluation boards, evaluating results and developing specifications for selecting next-generation components for deliverable systems.
• Developing and maintaining requirements documents, functional specification documents, interface control documents, etc.

Required Qualifications:

• At least 5 years of experience in hand on FPGA Design.
• Experience of RTL design with Verilog or SystemVerilog.
• Experience of bringing up and debugging FPGA based HW and FW.
• Experience developing and implementing FPGA-optimized versions of DSP algorithms.
• Experiencing in developing RTL Simulation and Verification environments.

Preferred Qualifications:

• Familiarity with modern Xilinx FPGA and SoC families and design tools (Ultrascale+, Ultrascale Zynq, RFSoC, Vivado, Xilinx IP cores)
• Experience with standard internal interfaces such as AXI4, AXI4-Stream, AXI4-Lite.
• Experience working with SoC designs such as Zynq and Zynq Ultrascale+ including architecting and interfacing with peripherals, interrupts, and related bus architectures.
• Familiarity with Xilinx Vivado and SDK.
• Experience with UVM verification methodology, developing test cases and test benches for FPGA design.