CAD DV team is looking for talented people with background in DV and SW skills, specific in ML/AI, to impact Apple DV engineers by innovating new ML based methods. These innovations are expected to make DV engineers day2day more effective and/or increasing its quality.
Key Qualifications
5+ years of experience in Verilog and System Verilog
Experienced with Synopsys VCS, NC-Verilog, or Models' - A must
Strong scripting abilities in PERL are needed; TCL or Python is a plus
Good communications skills are required and prior customer support experience is a plus
Experience writing or maintaining the script or Makefile that builds the simulation Program from RTL is a plus.
Familiarity with Verdi and/or DVE is considered a plus
Knowledge at C and C++ is a plus
Description
In this role you will work as part of the CAD DV team, innovating in CAD DV ML domain.
As CAD DV ML engineer you are expected to take active part in designing and researching ML/AI algorithms and be familiar with RTL and verification world.
Role involves debugging vendor tool problems.
Interacting with Verification teams to help solve their problems.
Implement new functionality to solve emerging problems or to optimize already existing methods.
Education & Experience
BSc/ MSc in Electrical Engineering or Computer Science.
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