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Principal Application Engineer

Overview
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Job TypeHybrid
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Experience5 years
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Job PositionSoftware
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UpdatedJun 29, 2024
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LocationPetah Tikva
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SalaryN/A
Skills
  • C C
  • C++ C++
  • 'e' ꞏ 5y
  • RTL ꞏ 5y
  • SV ꞏ 5y
  • TB Languages ꞏ 5y
  • UVM ꞏ 5y
  • Verilog ꞏ 5y
  • VHDL ꞏ 5y
  • Ethernet
  • PCIe
  • SATA
  • System-C
  • TLM
  • USB
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

  • BSc in Electrical engineering / Software engineering with distinction
  • Minimum of 5 years experience design/verification methodologies.
  • Experience with verification flows that include UVM.
  • Experience and knowledge of protocols like Ethernet, USB, SATA, PCIe (Not require all) – advantage.
  • Knowledge in RTL and TB Languages – Verilog or VHDL, SV or ‘e’ - Must
  • Knowledge in one or more of the following Languages: C / C++ / System-C / TLM for Design & Verification – advantage.
  • Team orientated, Good judgment under pressure
  • Fluent English

We’re doing work that matters. Help us solve what others can’t.
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