What will I be doing?

Role combines the leading a small team of excellent, experienced engineers, and a hands-on

design.

Responsibility for the new and legacy designs of both ASIC and FPGAs (Xilinx / Altera)

Work closely with the System, Alg , SW, HW, RF, CTO teams from IC definition, through chip

architecture, backend process till GDS, and manufacturing including verification and

validation.

Requirements:

Required Skills

Must have an experience with SoC Design through the entire VLSI flow.

Must have knowledge of Xilinx/Altera FPGA design flow and considerations.

High-level architecture definitions, micro architecture, Verilog writing and verification process

Including hands-on responsibility of writing and ownership on a complex Verilog blocks for

ASIC with performance, area and power constrains.

Qualified candidates must have:

• BSc in Electronics engineering/ MSEE advantage
• A minimum of 4 years of relevant experience of chip leading /VLSI team.
• A minimum of 6 additional years as VLSI Eng.
• Good understanding of ASIC and FPGA architecture, Verification methods and backend
  
  

flow

Advantage to applicants with:

• Knowledge and experience with video compression, video interfaces
• Knowledge and experience with MIMO OFDM modem architecture