Seeking an ASIC Leading Architect for a fast-growing startup.

Looking for a strong knowledgeable and experienced person in many aspects of the SoC design and implementation flow including the ability to define the chip’s architecture, block diagram, data bus, clocks, reset, interfaces, memories, pipe structure, verification, scan, production, testing, etc.

He/She should have a proven experience in high-speed high-performance topologies. Also needs to have knowledge in coverage, driven verification, and power.

He/She will be responsible for developing, contributing, and leading ASIC architecture activities.

Seeking for a highly motivated candidate with strong communication skills (expected to work closely with all the design teams), pay attention to details and quality oriented.

Responsibilities Include (But Not Limited To)

• Defining requirements for ASIC specifications, protocol analysis, design, verification, and physical implementation teams
• Evaluating area, performance, power, and ease-of-implementation trade-offs between different implementation solutions
• Perform research and analysis for future architectures
• Reviewing and configuring 3rd party IPs
• Supporting other teams in the ASIC organization and reviewing their work
• Collaborate with different teams in the company (physical design, logic design, verification, firmware, algorithm, system, etc.)
• Continuously finding opportunities for improving design quality and design practices
  
  

Requirements:

Minimum Qualifications

• Bachelor or master’s degree in electrical engineering or equivalent
• 10+ years of ASIC experience, minimum 4 years of SOC Architecture experience
• Knowledge and experience in various aspects of SoC design, verification, and implementation flows
• Experience with low-power design techniques
• Scripting and Unix shell language experience: e.g., Perl, Python, Unix shell scripts
• Ability to read and understand SW code
  
  

Preferred Skills

• Matlab
• Knowledge in Ethernet communication layer – PCS, PMD, etc.
• Error correction knowledge
• RTL design experience in Verilog/SystemVerilog
• Experience with HW modeling languages
• ASIC architecture experience in data center communication solutions
• Design/architecture experience with high-speed serial and parallel interfaces (e.g., SERDES, DAC, ADC)